The above-referenced Yamanouchi et al. U.S. application Ser. No. 546,376 discloses a structured integrated circuit design methodology with particular applicability to two-phase logic design. The methodology is based on describing a logic function using a high level behavioral description flowchart, properly sizing devices to be used in the circuit for speed, and reducing trial and error in circuit layout implementation using novel chip planning techniques.
The Yamanouchi et al. methodology begins with the definition of signal types based on both the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A set of rules is then established for use of the signal types. Next, the inputs and outputs of the logic function are defined and utilized to create a behavioral flowchart using defined symbols. An associated database is then created that defines the parameters of the various elements of the flowchart. The flowchart is then converted to a logic diagram, either by coded state assignment or by direct implementation. The resulting logic diagram is then analyzed for speed utilizing a Figures of Merit (FOM) technique for establishing device sizes. The resulting circuit design may then be carried through to layout utilizing conventional computer aided design (CAD) tools.
While the Yamanouchi et al. methodology provides a unique design technique that improves vastly on the prior art, it can result in a flowchart that includes repetitive information. This is particularly true for complex sequential processing circuits. This repetitive information consumes a large area on the flowchart and makes it difficult to read.